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general description the max17040/max17041 are ultra-compact, low-cost, host-side fuel-gauge systems for lithium-ion (li+) batter- ies in handheld and portable equipment. the max17040 is configured to operate with a single lithium cell and the max17041 is configured for a dual-cell 2s pack. the max17040/max17041 use a sophisticated li+ bat- tery-modeling scheme, called modelgauge to track the battery? relative state-of-charge (soc) continuously over a widely varying charge/discharge profile. unlike traditional fuel gauges, the modelgauge algorithm elim- inates the need for battery relearn cycles and an exter- nal current-sense resistor. temperature compensation is possible in the application with minimal interaction between a ? and the device. a quick-start mode provides a good initial estimate of the battery? soc. this feature allows the ic to be located on system side, reducing cost and supply chain constraints on the battery. measurement and esti- mated capacity data sets are accessed through an i 2 c interface. the max17040/max17041 are available in either a 0.4mm pitch 9-bump ucsp or 2mm x 3mm, 8-pin tdfn lead-free package. applications features ? host-side or battery-side fuel gauging 1 cell (max17040) 2 cell (max17041) ? precision voltage measurement ?2.5mv accuracy to 5.00v (max17040) ?0mv accuracy to 10.00v (max17041) ? accurate relative capacity (rsoc) calculated from modelgauge algorithm ? no offset accumulation on measurement ? no full-to-empty battery relearning necessary ? no sense resistor required ? 2-wire interface ? low power consumption ? tiny, lead(pb)-free, 8-pin, 2mm x 3mm tdfn package or tiny 0.4mm pitch 9-bump ucsp package max17040/max17041 compact, low-cost 1s/2s fuel gauges ________________________________________________________________ maxim integrated products 1 ordering information cell 1 f 1k 10nf 150 gnd ep ctg scl sda eo seo v dd system p i 2 c bus master li+ protection circuit max17040 max17041 simplified operating circuit 19-5210; rev 6; 8/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max17040 g+u -20c to +70c 8 tdfn-ep* max17040g+t -20c to +70c 8 tdfn-ep* max17040x+u -20c to +70c 9 ucsp max17040x+t10 -20c to +70c 9 ucsp max17041 g+u -20c to +70c 8 tdfn-ep* max17041g+t -20c to +70c 8 tdfn-ep* max17041x+ -20c to +70c 9 ucsp max17041x+t10 -20c to +70c 9 ucsp + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. * ep = exposed pad. pin configurations appear at end of data sheet. smart phones mp3 players digital still cameras digital video cameras portable dvd players gps systems handheld and portable applications modelgauge is a trademark of maxim integrated products, inc. ucsp is a trademark of maxim integrated products, inc.
max17040/max17041 compact, low-cost 1s/2s fuel gauges 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (2.5v v dd 4.5v, t a = -20? to +70?, unless otherwise noted. contact maxim for v dd greater than 4.5v.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on ctg pin relative to gnd .....................-0.3v to +12v voltage on cell pin relative to gnd....................-0.3v to +12v voltage on all other pins relative to gnd...............-0.3v to +6v operating temperature range ...........................-40? to +85? power dissipation ..........1333mw at +70? (derate 16.7mw/?) storage temperature range (t a = 0? to +70? (note 10))........................-55? to +125? lead temperature (tdfn only, soldering, 10s) ..............+300? soldering temperature (reflow) tdfn .............................................................................+260? ucsp.............................................................................+240? parameter symbol conditions min typ max units with on-chip clock in use 50 75 active current i active with external 32khz clock 40 65 a v dd = 2.0v 0.5 1.0 sleep-mode current (note 2) i sleep 1 3 a v dd = 3.6v at +25 c -1 +1 t a = 0 c to +70 c (note 10) -2 +2 time-base accuracy (note 3) t err t a = -20 c to +70 c -3 +3 % t a = +25 c, v in = v dd -12.5 +12.5 max17040 voltage- measurement error -30 +30 t a = +25 c, 5.0v < v in < 9.0v -30 +30 max17041 voltage- measurement error v gerr 5.0v < v in < 9.0v -60 +60 mv cell pin input impedance r cell 15 m input logic-high: scl, sda, eo, seo v ih (note 1) 1.4 v input logic-low: scl, sda, eo, seo v il (note 1) 0.5 v output logic-low: sda v ol i ol = 4ma (note 1) 0.4 v pulldown current: scl, sda i pd v dd = 4.5v, v pin = 0.4v 0.2 a input capacitance: eo c bus 50 pf bus low timeout t sleep (note 4) 1.75 2.5 s electrical characteristics recommended dc operating conditions (2.5v v dd 4.5v, t a = -20? to +70?, unless otherwise noted.) parameter symbol conditions min typ max units supply voltage v dd (note 1) +2.5 +4.5 v data i/o pins scl, sda, eo, seo (note 1) -0.3 +5.5 v max17040 cell pin v cell (note 1) -0.3 +5.0 v max17041 cell pin v cell (note 1) -0.3 +10.0 v
max17040/max17041 compact, low-cost 1s/2s fuel gauges _______________________________________________________________________________________ 3 note 1: all voltages are referenced to gnd. note 2: sda, scl = gnd; eo, seo idle. note 3: external time base on eo pin must meet this specification. note 4: the max17040/max17041 enter sleep mode 1.75s to 2.5s after (scl < v il ) and (sda < v il ). note 5: f scl must meet the minimum clock low time plus the rise/fall times. note 6: the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. note 7: this device internally provides a hold time of at least 75ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 8: filters on sda and scl suppress noise spikes at the input buffers and delay the sampling instant. note 9: c b ?otal capacitance of one bus line in pf. note 10: applies to 8-pin tdfn-ep package type only. parameter symbol conditions min typ max units scl clock frequency f scl (note 5) 0 400 khz bus free time between a stop and start condition t buf 1.3 s hold time (repeated) start condition t hd:sta (note 5) 0.6 s low period of scl clock t low 1.3 s high period of scl clock t high 0.6 s setup time for a repeated start condition t su:sta 0.6 s data hold time t hd:dat (notes 6, 7) 0 0.9 s data setup time t su:dat (note 6) 100 ns rise time of both sda and scl signals t r 20 + 0.1c b 300 ns fall time of both sda and scl signals t f 20 + 0.1c b 300 ns setup time for stop condition t su:sto 0.6 s spike pulse widths suppressed by input filter t sp (note 8) 0 50 ns capacitive load for each bus line c b (note 9) 400 pf scl, sda input capacitance c bin 60 pf electrical characteristics: 2-wire interface (2.5v v dd 4.5v, t a = -20? to +70?.)
max17040/max17041 compact, low-cost 1s/2s fuel gauges 4 _______________________________________________________________________________________ typical operating characteristics (t a = +25?, unless otherwise noted.) quiescent current vs. supply voltage max17040 toc01 v dd (v) quiescent current ( a) 3 245 1 20 40 60 80 100 0 0 t a = +70 c t a = +25 c t a = -20 c simple c/2 rate cycles* soc accuracy max17040 toc02 time (hr) state of charge (%) soc error (%) 12 10 68 4 2 10 20 30 40 50 60 70 80 90 100 0 -8 -6 -4 -2 0 2 4 6 8 10 -10 0 error (%) max17040/ max17041 soc: dashed line reference soc: solid line c/2 rate zigzag pattern* soc accuracy max17040 toc05 time (hr) state of charge (%) soc error (%) 12 81622 20 4 10 20 30 40 50 60 70 80 90 100 0 -8 -6 -4 -2 0 2 4 6 8 10 -10 0 error (%) max17040/max17041 soc: dashed line reference soc: solid line simple c/4 rate cycles* soc accuracy max17040 toc03 time (hr) state of charge (%) soc error (%) 12 10 68 18 16 22 20 14 4 2 10 20 30 40 50 60 70 80 90 100 0 -8 -6 -4 -2 0 2 4 6 8 10 -10 0 error (%) max17040/ max17041 soc: dashed line reference soc: solid line max17040 voltage adc error vs. temperature max17040 toc04 temperature ( c) voltage adc error (mv) 35 10 60 85 -15 -15 -10 -5 0 5 10 15 20 -20 -40 v cell = 3.0v v cell = 4.2v v cell = 3.6v * sample accuracy with custom configuration data programmed into the ic.
max17040/max17041 compact, low-cost 1s/2s fuel gauges _______________________________________________________________________________________ 5 sda scl t f t low t hd:sta t hd:dat t su:sta t su:sto t su:dat t hd:sta t sp t r t buf t r t f ssr p s figure 1. 2-wire bus timing diagram pin description pin ucsp tdfn name function a1 8 sda serial data input/output. open-drain 2-wire data line. connect this pin to the data signal of the 2-wire interface. this pin has a 0.2a typical pulldown to sense disconnection. a2 7 scl serial clock input. input only 2-wire clock line. connect this pin to the clock signal of the 2-wire interface. this pin has a 0.2a typical pulldown to sense disconnection. a3 1 ctg connect to ground. connect to vss during normal operation. b1 6 eo external 32khz clocking signal. input for external clocking signal to be the primary system clock. configured to implement interrupt feature with a pulldown set on seo pin. b2 n.c. no connect. do not connect. b3 2 cell battery-voltage input. the voltage of the cell pack is measured through this pin. c1 5 seo external 32khz clocking signal enable input. input to enable external clocking signal on eo pin with a pullup state; a pulldown state to configure the interrupt feature. external 32khz clock enable. connects logic-low to enable external interrupt. c2 3 v dd power-supply input. 2.5v to 4.5v input range. connect to system power through a decoupling network. connect a 10nf typical decoupling capacitor close to pin. c3 4 gnd ground. connect to the negative power rail of the system. ep exposed pad (tdfn only). connect to ground. state machine (soc, rate) 2-wire interface ic ground time base (32khz) adc (vcell) voltage reference bias gnd cell v dd scl sda ctg seo eo max17040 max17041 figure 2. block diagram detailed description figure 1 shows the 2-wire bus timing diagram, and figure 2 is the max17040/max17041 block diagram. modelgauge theory of operation the max17040/max17041 use a sophisticated battery model, which determines the soc of a nonlinear li+ battery. the model effectively simulates the internal dynamics of a li+ battery and determines the soc. the model considers the time effects of a battery caused by the chemical reactions and impedance in the battery. the max17040/max17041 soc calculation does not accumulate error with time. this is advantageous
max17040/max17041 compared to traditional coulomb counters, which suffer from soc drift caused by current-sense offset and cell self-discharge. this model provides good performance for many li+ chemistry variants across temperature and age. to achieve optimum performance, the max17040/max17041 must be programmed with con- figuration data custom to the application. contact the factory for details. fuel-gauge performance the classical coulomb-counter-based fuel gauges suf- fer from accuracy drift due to the accumulation of the offset error in the current-sense measurement. although the error is often very small, the error increases over time in such systems, cannot be eliminated, and requires periodic corrections. the corrections are usu- ally performed on a predefined soc level near full or empty. some other systems use the relaxed battery voltage to perform corrections. these systems deter- mine the true soc based on the battery voltage after a long time of no activity. both have the same limitation: if the correction condition is not observed over time in the actual application, the error in the system is boundless. in some systems, a full charge/discharge cycle is required to eliminate the drift error. to determine the true accuracy of a fuel gauge, as experienced by end users, the battery should be exercised in a dynamic manner. the end-user accuracy cannot be understood with only simple cycles. the max17040/max17041 do not suffer from the drift problem since they do not rely on the current information. ic power-up when the battery is first inserted into the system, there is no previous knowledge about the battery? soc. the ic assumes that the battery has been in a relaxed state for the previous 30min. the first a/d voltage measurement is translated into a best ?irst guess?for the soc. initial error caused by the battery not being in a relaxed state fades over time, regardless of cell loading following this initial conversion. because the soc determination is conver- gent rather than divergent (as in a coulomb counter), this initial error does not have a long-lasting impact. quick-start a quick-start allows the max17040/max17041 to restart fuel-gauge calculations in the same manner as initial power-up of the ic. for example, if an application? power-up sequence is exceedingly noisy such that excess error is introduced into the ic? ?irst guess?of soc, the host can issue a quick-start to reduce the error. a quick-start is initiated by a rising edge on the eo pin when seo is logic-low, or through software by writing 4000h to the mode register. external oscillator control when the seo pin is logic-high, the max17040/ max17041 disable the 32khz internal oscillator and rely on external clocking from the eo pin. a precision exter- nal clock source reduces current consumption during normal operation. when the seo pin is logic-low, the eo pin becomes an interrupt input. any rising edge detected on eo causes the max17040/max17041 to initiate a quick-start. sleep mode holding both sda and scl logic-low forces the max17040/max17041 into sleep mode. while in sleep mode, all ic operations are halted and power drain of the ic is greatly reduced. after exiting sleep mode, fuel-gauge operation continues from the point it was halted. sda and scl must be held low for at least 2.5s to guarantee transition into sleep mode. afterwards, a rising edge on either sda or scl immediately transi- tions the ic out of sleep mode. power-on reset (por) writing a value of 5400h to the command register caus- es the max17040/max17041 to completely reset as if power had been removed. the reset occurs when the last bit has been clocked in. the ic does not respond with an i 2 c ack after this command sequence. registers all host interaction with the max17040/max17041 is handled by writing to and reading from register loca- tions. the max17040/max17041 have six 16-bit regis- ters: soc , vcell , mode , version , rcomp , and command . register reads and writes are only valid if all 16 bits are transferred. any write command that is terminated early is ignored. the function of each regis- ter is described as follows. all remaining address loca- tions not listed in table 1 are reserved. data read from reserved locations is undefined. compact, low-cost 1s/2s fuel gauges 6 _______________________________________________________________________________________
vcell register battery voltage is measured at the cell pin input with respect to gnd over a 0 to 5.00v range for the max17040 and 0 to 10.00v for the max17041 with res- olutions of 1.25mv and 2.50mv, respectively. the a/d calculates the average cell voltage for a period of 125ms after ic por and then for a period of 500ms for every cycle afterwards. the result is placed in the vcell register at the end of each conversion period. figure 3 shows the vcell register format. soc register the soc register is a read-only register that displays the state of charge of the cell as calculated by the modelgauge algorithm. the result is displayed as a percentage of the cell? full capacity. this register automatically adapts to variation in battery size since the max17040/max17041 naturally recognize relative soc. units of % can be directly determined by observ- ing only the high byte of the soc register. the low byte provides additional resolution in units 1/256%. the reported soc also includes residual capacity, which might not be available to the actual application because of early termination voltage requirements. when soc() = 0, typical applications have no remaining capacity. the first update occurs within 250ms after por of the ic. subsequent updates occur at variable intervals depending on application conditions. modelgauge cal- culations outside the register are clamped at minimum and maximum register limits. figure 4 shows the soc register format. max17040/max17041 compact, low-cost 1s/2s fuel gauges _______________________________________________________________________________________ 7 address (hex) register description read/ write default (hex) 02hC03h vcell reports 12-bit a/d measurement of battery voltage. r 04hC05h soc reports 16-bit soc result calculated by modelgauge algorithm. r 06hC07h mode sends special commands to the ic. w 08hC09h version returns ic version. r 0chC0dh rcomp battery compensation. adjusts ic performance based on application conditions. r/w 9700h fehCffh command sends special commands to the ic. w table 1. register summary msb?address 02h lsb?address 03h 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 0 0 0 0 msb lsb msb lsb 0: bits always read logic 0 units: 1.25mv for max17040 2.50mv for max17041 figure 3. vcell register format msb?address 04h lsb?address 05h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 msb lsb msb lsb units: 1.0% figure 4. soc register format
max17040/max17041 compact, low-cost 1s/2s fuel gauges 8 _______________________________________________________________________________________ mode register the mode register allows the host processor to send special commands to the ic (figure 4). valid mode register write values are listed as follows. all other mode register values are reserved. table 2 shows the mode register command. version register the version register is a read-only register that con- tains a value indicating the production version of the max17040/max17041. rcomp register rcomp is a 16-bit value used to compensate the modelgauge algorithm. rcomp can be adjusted to optimize performance for different lithium chemistries or different operating temperatures. contact maxim for instructions for optimization. the factory-default value for rcomp is 9700h. command register the command register allows the host processor to send special commands to the ic. valid command register write values are listed as follows. all other command register values are reserved. table 3 shows the command register command. application examples the max17040/max17041 have a variety of configura- tions, depending on the application. table 4 shows the most common system configurations and the proper pin connections for each. figure 5 shows an example application for a 1s cell pack. the max17040 is mounted on the system side and powered directly from the cell pack. the external rc networks on v dd and cell provide noise filtering of the ic power supply and a/d measurement. in this example, the seo pin is connected to v dd to allow an external clock and reduce power usage by the max17040. the system? 32khz clock is connected to the eo input pin. figure 6 shows a max17041 example application using a 2s cell pack. the max17041 is mounted on the sys- tem side and powered from a 3.3v supply generated by the system. the cell pin is still connected directly to pack+ through an external noise filter. the seo pin is connected low to allow the system hardware to reset the fuel gauge. after power is supplied, the system watchdog generates a low-to-high transition on the eo pin to signal the max17041 to perform a quick-start. value command description 4000h quick-start see the quick-start description section. table 2. mode register command value command description 5400h por see the power-on reset (por) description section. table 3. command register command system configuration ic v dd seo eo 1s pack-side location max17040 power directly from battery connect to gnd connect to gnd 1s host-side location max17040 power directly from battery connect to gnd connect to gnd 1s host-side location, external clocking max17040 power directly from battery connect to v dd connect to precision 32khz clock source 1s host-side location, hardware quick-start max17040 power directly from battery connect to gnd connect to rising- edge reset signal 2s pack-side location max17041 power from 2.5v to 4.5v ldo in pack connect to gnd connect to gnd 2s host-side location max17041 power from 2.5v to 4.5v ldo or pmic connect to gnd connect to gnd 2s host-side location, external clocking max17041 power from 2.5v to 4.5v ldo or pmic connect to v dd connect to precision 32khz clock source 2s host-side location, hardware quick-start max17041 power from 2.5v to 4.5v ldo or pmic connect to gnd connect to rising- edge reset signal table 4. possible application configurations
max17040/max17041 compact, low-cost 1s/2s fuel gauges _______________________________________________________________________________________ 9 2-wire bus system the 2-wire bus system supports operation as a slave- only device in a single or multislave, and single or multi- master system. slave devices can share the bus by uniquely setting the 7-bit slave address. the 2-wire interface consists of a serial data line (sda) and serial clock line (scl). sda and scl provide bidirectional communication between the max17040/max17041 slave device and a master device at speeds up to 400khz. the max17040/max17041s?sda pin operates bidirectionally; that is, when the max17040/max17041 receive data, sda operates as an input, and when the max17040/max17041 return data, sda operates as an open-drain output, with the host system providing a resistive pullup. the max17040/max17041 always operate as a slave device, receiving and transmitting data under the control of a master device. the master initiates all transactions on the bus and generates the scl signal, as well as the start and stop bits, which begin and end each transaction. 10nf cell seo sda gnd scl ep pack- pack+ protection ic (li+/polymer) system gnd system v dd battery system v dd ctg 1k 150 eo system p 1 f 32khz oscillator output i 2 c bus master max17040 figure 5. max17040 application example with external clock cell seo sda gnd ep scl pack- pack+ protection ic (li+/polymer) battery system v dd ctg 1k eo system pmic system p 1 f watchdog 3.3v output i 2 c bus master max17041 system gnd system v dd figure 6. max17041 application example with hardware reset
max17040/max17041 bit transfer one data bit is transferred during each scl clock cycle, with the cycle defined by scl transitioning low to high and then high to low. the sda logic level must remain stable during the high period of the scl clock pulse. any change in sda when scl is high is inter- preted as a start or stop control signal. bus idle the bus is defined to be idle, or not busy, when no master device has control. both sda and scl remain high when the bus is idle. the stop condition is the proper method to return the bus to the idle state. start and stop conditions the master initiates transactions with a start condi- tion (s) by forcing a high-to-low transition on sda while scl is high. the master terminates a transaction with a stop condition (p), a low-to-high transition on sda while scl is high. a repeated start condition (sr) can be used in place of a stop then start sequence to terminate one transaction and begin another without returning the bus to the idle state. in multimaster sys- tems, a repeated start allows the master to retain control of the bus. the start and stop conditions are the only bus activities in which the sda transitions when scl is high. acknowledge bits each byte of a data transfer is acknowledged with an acknowledge bit (a) or a no-acknowledge bit (n). both the master and the max17040 slave generate acknowl- edge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until scl returns low. to generate a no acknowl- edge (also called nak), the receiver releases sda before the rising edge of the acknowledge-related clock pulse and leaves sda high until scl returns low. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer can occur if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication. data order a byte of data consists of 8 bits ordered most signifi- cant bit (msb) first. the least significant bit (lsb) of each byte is followed by the acknowledge bit. the max17040/max17041 registers composed of multibyte values are ordered msb first. the msb of multibyte reg- isters is stored on even data-memory addresses. slave address a bus master initiates communication with a slave device by issuing a start condition followed by a slave address (saddr) and the read/write (r/w) bit. when the bus is idle, the max17040/max17041 contin- uously monitor for a start condition followed by its slave address. when the max17040/max17041 receive a slave address that matches the value in the slave address register, it responds with an acknowledge bit during the clock period following the r/w bit. the 7-bit slave address is fixed to 6ch (write)/ 6dh (read): read/write bit the r/w bit following the slave address determines the data direction of subsequent bytes in the transfer. r/w = 0 selects a write transaction, with the following bytes being written by the master to the slave. r/w = 1 selects a read transaction, with the following bytes being read from the slave by the master. bus timing the max17040/max17041 are compatible with any bus timing up to 400khz. no special configuration is required to operate at any speed. 2-wire command protocols the command protocols involve several transaction for- mats. the simplest format consists of the master writing the start bit, slave address, r/w bit, and then monitor- ing the acknowledge bit for presence of the max17040/ max17041. more complex formats, such as the write data and read data, read data and execute device-spe- cific operations. all bytes in each command format require the slave or host to return an acknowledge bit before continuing with the next byte. table 5 shows the key that applies to the transaction formats. max17040/max17041 slave address 0110110 compact, low-cost 1s/2s fuel gauges 10 ______________________________________________________________________________________
basic transaction formats a write transaction transfers 2 or more data bytes to the max17040/max17041. the data transfer begins at the memory address supplied in the maddr byte. control of the sda signal is retained by the master throughout the transaction, except for the acknowledge cycles: a read transaction transfers 2 or more bytes from the max17040/max17041. read transactions are com- posed of two parts, a write portion followed by a read portion, and are therefore inherently longer than a write transaction. the write portion communicates the starting point for the read operation. the read portion follows immediately, beginning with a repeated start, slave address with r/w set to a 1. control of sda is assumed by the max17040/max17041, beginning with the slave address acknowledge cycle. control of the sda signal is retained by the max17040/max17041 throughout the transaction, except for the acknowledge cycles. the master indicates the end of a read transaction by responding to the last byte it requires with a no acknowledge. this signals the max17040/max17041 that control of sda is to remain with the master following the acknowledge clock. write data protocol the write data protocol is used to write to register to the max17040/max17041 starting at memory address maddr. data0 represents the data written to maddr, data1 represents the data written to maddr + 1, and datan represents the last data byte, written to maddr + n. the master indicates the end of a write transaction by sending a stop or repeated start after receiving the last acknowledge bit: the msb of the data to be stored at address maddr can be written immediately after the maddr byte is acknowledged. because the address is automatically incremented after the lsb of each byte is received by the max17040/max17041, the msb of the data at address maddr + 1 can be written immediately after the acknowledgment of the data at address maddr. if the bus master continues an autoincremented write transaction beyond address 4fh, the max17040/ max17041 ignore the data. a valid write must include both register bytes. data is also ignored on writes to read-only addresses. incomplete bytes and bytes that are not acknowledged by the max17040/max17041 are not written to memory. read data protocol the read data protocol is used to read to register from the max17040/max17041 starting at the memory address specified by maddr. both register bytes must be read in the same transaction for the register data to be valid. data0 represents the data byte in memory location maddr, data1 represents the data from maddr + 1, and datan represents the last byte read by the master: data is returned beginning with the msb of the data in maddr. because the address is automatically incre- mented after the lsb of each byte is returned, the msb of the data at address maddr + 1 is available to the host immediately after the acknowledgment of the data at address maddr. if the bus master continues to read beyond address ffh, the max17040/max17041 output data values of ffh. addresses labeled reserved in the memory map return undefined data. the bus master terminates the read transaction at any byte boundary by issuing a no acknowledge followed by a stop or repeated start. s. saddr w. a. maddr. a. sr. saddr r. a. data0. a. data1. a... datan. n. p saddr w. a. maddr. a. data0. a. data1. a... datan. a read: s. saddr w. a. maddr. a. sr. saddr r. a. data0. a. data1. n. p write portion read portion write: s. saddr w. a. maddr. a. data0. a. data1. a. p max17040/max17041 compact, low-cost 1s/2s fuel gauges ______________________________________________________________________________________ 11 key description key description s start bit sr repeated start saddr slave address (7 bit) w r/w bit = 0 maddr memory address byte p stop bit data data byte written by master data data byte returned by slave a acknowledge bitmaster a acknowledge bitslave n no acknowledgemaster n no acknowledgeslave table 5. 2-wire protocol key
max17040/max17041 compact, low-cost 1s/2s fuel gauges 12 ______________________________________________________________________________________ 1 + 34 865 sda eo seo 2 7 scl ctg v dd gnd cell tdfn (2mm 3mm) top view max17040 max17041 top view bump side down sda scl ctg eo n.c. cell seo v dd gnd + ucsp 123 b c a max17040 max17041 pin configurations package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per tains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 tdfn t823+1 21-0174 90-0091 9 ucsp w91c1+1 21-0459 refer to application note 1891
max17040/max17041 compact, low-cost 1s/2s fuel gauges maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/08 initial release 1 10/08 ? corrected the order of the pins in the pin configuration ? changed the max operating voltage from 5.5v to 4.5v ? inserted the cell pin input impedance specification into the dc electrical characteristics table ? corrected the order of the pins in the pin description table and changed the max operating voltage for the v dd pin 1, 2, 3, 5, 8 23/09 ? added the following sentence to the registers section: register reads and writes are only valid if all 16 bits are transferred ? added the following sentence to the write data protocol section: a valid write must include both register bytes ? added the following sentence to the read data protocol section: both register bytes must be read in the same transaction for the register data to be valid 6, 11 3 4/10 exposed pad connection to ground in figures 5 and 6; corrected errors in specifications 1, 2, 7, 9, 13 4 8/10 changed v cell pin external register value; added description and ordering information for ucsp package type 1, 2, 3, 5, 9, 12, 13 5 10/10 updated ordering information table 1, 2, 5, 12, 13 6 8/11 corrected time from start up until soc valid; added text indicating accurate results require custom configuration for each application 4, 6, 7, 13

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